(1) Field of the Invention
The present invention generally relates to a method for forming low temperature polysilicon thin film transistor, and particularly, to a method for forming low temperature polysilicon thin film transistor with a low doped drain structure.
(2) Description of the Prior Art
Thin film transistor-liquid crystal display (TFT-LCD) is currently the most popular product in the display market. The liquid crystal display technology grows fast, and competition in this art is very intense. The know how about enhancing efficiency and reliability of thin film transistor and about cost down are all the most important issues today. To enhance efficiency of thin film transistor, developing new material or advanced structure are both the practicable ways. Considering that “leakage current” is a major reason of power-waste, using silicon insulating layer, high-K gate or other skills to reduce the leakage current are the known solutions. As to the structural solution, one remarkable technique is doping low concentration ions at the intra-gate region of thin film transistor, which is capable of reducing transverse electrical resistance and resulting in high efficiency thin film transistor, namely low temperature polysilicon thin film transistor with low doped drain structure.
Referring to FIG.1A and FIG. 1B, which illustrate a method for forming a low temperature polysilicon thin film transistor with a low doped drain structure according to a prior art. As shown in FIG. 1A, a substrate 10, which is transparent and insulated, is firstly provided. A polysilicon island 12 is further formed on the substrate 10. Then, a dielectric layer 14 is deposited to cover with the polysilicon island 12. In prior arts, a photo-resist patterned layer 16 is formed on the dielectric layer 14. Following, a high concentration ion-doping is performed using the photo resist patterned layer 16 as mask, so as to form heavily doped region 123 (either N+ region or P+ region). And the other region of the polysilicon island 12 right beneath the photo-resist patterned layer 16 is an un-doped region 121.
As shown in FIG. 1B, after the photo-resist patterned layer 16 is removed, a gate 18 is defined and formed on the dielectric layer 14. The gate 18 has a width smaller than the photo-resist patterned layer 16. Then, a low concentration ion-doping is performed using the gate 18 as mask, so as to form low doped region 122 (either N− region or P− region). Thus, mentioned low doped drain structure is completed, and the remaining un-doped region 121 right beneath the gate 18 is used as channel within the thin film transistor.
Accordingly, the prior method for forming low temperature polysilicon thin film transistor with low doped drain structure needs at least one added photo mask to define and form the photo-resist patterned layer 16. The added photo mask not only brings external cost, it also leads to a complicated fabrication process. Besides, during the photo etching process, aligning inaccuracy usually results in shifting of the low doped drain structure, and yield is thus limited. Therefore, a fabrication method without added photo mask is greatly desired.